Semiconductor device having gate trench and manufacturing method thereof

ABSTRACT

Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench. The cap insulating film has substantially the same planer shape as that of the conductive film.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of application Ser. No. 13/485,282 filedon May 31, 2012, which claims foreign priority to Japanese ApplicationNo. 2011-123233 filed on Jun. 1, 2011. The entire contents of each ofthe above applications are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method offorming a semiconductor device.

2. Description of Related Art

Recently, dimensions of transistors have become smaller due tominiaturization of semiconductor elements. The dimensional reductions ofthe transistors will cause remarkable short channel effects of thetransistors. As the dimensions of memory cells in dynamic random accessmemories (DRAMs) and the like are reduced, the channel lengths oftransistors are also reduced, which may cause degradation of theperformance of transistors. The deterioration in retention of memorycells or writing characteristics has been problematic.

In view of the above, recess (trench) field effect transistors (FETs),fin FETs, and the like have been developed. The recess (trench) FET hasa structure in which a trench (also called a groove) is formed in asemiconductor substrate to obtain a channel having a three-dimensionalstructure. Japanese Unexamined Patent Application, First Publications,Nos. JP-A-2005-064500, JP-A-2007-027753, and JP-A-2007-305827 disclosethat the fin FET has a structure in which a fin is formed betweentrenches to obtain a channel having a three-dimensional structure.

The trench FET is formed by forming a trench in a semiconductorsubstrate and forming a gate electrode within the trench while a gateinsulating film is interposed between the gate electrode and thesemiconductor substrate. A channel of the trench FET has athree-dimensional structure. The fin FET is formed by forming a gateelectrode over a gate insulting film so as to cross over a finprotruding from a bottom surface of the trenches formed in thesemiconductor substrate. Consequently, the channel has athree-dimensional structure. In any case, it is possible to suppress theshort channel effects because the gate length can be lengthened withrespect to the channel width.

A study has been carried out to adopt buried gate transistors forselecting transistors included in memory cells in the DRAMs due toreduction in size of the memory cell. The buried gate transistor has astructure in which a gate electrode is buried in the semiconductorsubstrate.

The gate electrode of the buried gate transistor does not protrude fromthe surface of the substrate because the gate electrode (word line) isburied in the semiconductor substrate. Among wirings connected to memorycells, only bit lines are located over the semiconductor substrate. Thiswill increase flexibility of layouts of capacitors, contact plugs, andthe like, which are included in the memory cell and formed over thesemiconductor substrate. This will reduce the difficulty of processingthe capacitors, the contact plugs, and the like.

A transistor as shown in FIG. 18 has the channel of thethree-dimensional structure described above. The transistor is formed asfollows. An isolation region 101 and an active region 102 are formed ina surface portion of a semiconductor substrate 100. Trench portions 103and 104 for a buried gate electrode are formed in the isolation region101 and the active region 102, respectively. A fin portion 107 is aprotrusion which is a part of the active region 102 between the trenchportions 103. A saddle fin gate electrode 106 is formed by burying aconductive material in the trench portions 103 and 104 while a gateinsulating film 105 is interposed between the saddle fin gate electrode106 and the semiconductor substrate. That is, the saddle fin gateelectrode 106 crosses over the fin portion 107. An upper surface 107 aof the fin portion 107 is located to be higher than a bottom surface ofthe trench portion 103 and to be lower than an upper surface of theactive region 102 (an upper surface of the semiconductor substrate 100).This is because the trench portion 104 in the active region 102 isshallower than the trench portion 103 formed in the isolation region102. A source region 108 a and a drain region 108 b (impurity diffusionlayers) are formed, by implanting ions, in two active regions 102between which the gate electrode 106 is interposed.

However, widths of the trench portions 103 and 104 for the buried gateelectrode become narrow due to the reduction in dimensions of the memorycell described above. Thus, widths of channel regions formed in theupper surface 107 a and a side surface 107 b of the fin portion 107 alsobecome narrow in correspondence with the widths of the buried gatetrench portions 103 and 104. Therefore, in some cases, it is difficultto sufficiently secure an ON current due to a short channel effect.

SUMMARY

In one embodiment, there is provided a manufacturing method of asemiconductor device that includes: forming a plurality of elementisolation regions extending in a first direction in parallel on asemiconductor substrate so that a plurality of active regions eachsandwiched between adjacent two of the element isolation regions aredefined in the semiconductor substrate, each of the element isolationregions having an element isolation insulating film filling an isolationtrench formed in the semiconductor substrate, and the active regionsbeing arranged at a predetermined pitch in a second directionintersecting with the first direction; forming a plurality of gatetrenches extending in the second direction across the element isolationregions and the active regions, each of the gate trenches having aplurality of first trench portions crossing the active regions and aplurality of second trench portions crossing the element isolationregions, the first trench portions having bottom surfaces positioned athigher than bottom surfaces of the second trench portions so that eachof the active regions have a plurality of first fin portions formed onthe bottom surfaces of the first trench portions protruding with respectto the bottom surfaces of the second trench portions, and the secondtrench portions having a width in the first direction wider than a widthof the first trench portions in the first direction so that each of theactive regions have a plurality of second fin portions formed on sidesurfaces of the first trench portions protruding with respect to theside surfaces of the second trench portions; forming a plurality ofconductive films each buries a lower portion of an associated one of thegate trenches; and forming a plurality of cap insulating films eachcovers an upper surface of an associated one of the conductive films sothat the cap insulating films bury upper portions of the gate trenches.

In another embodiment, there is provided a manufacturing method of asemiconductor device that includes: forming first and second elementisolation regions extending in a first direction in a semiconductorsubstrate so that an active region of the semiconductor substratesandwiched between the first and second element isolation regions in asecond direction intersecting with the first direction is defined;forming first and second films extending in the second direction overthe first and second element isolation regions and the active region,each of the first and second films having a lower film and an upperfilm; anisotropic etching the first and second element isolation regionsand the active region using the upper films as an etching mask so that afirst trench portion is formed in the active region and second trenchportions are formed in the first and second element isolation regions;removing the upper films so that the lower films are exposed; andisotropic etching the first and second element isolation regions and thelower films so that a first fin portion is formed on a bottom surface ofthe first trench portions protruding with respect to bottom surfaces ofthe second trench portions, and so that second fin portions are formedon side surfaces of the first trench portions protruding with respect toside surfaces of the second trench portions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are views indicative of an embodiment of a semiconductordevice to which the present invention applies, in which FIG. 1A is aplan view of the semiconductor device 100, FIG. 1B is an enlargedbird's-eye view of a main part of the semiconductor device 100, and FIG.1C is a cross sectional view indicative of an embodiment of a channelstructure;

FIGS. 2A to 2C are graphs indicative of results of comparing betweenelectrical characteristics of the semiconductor device to which thepresent invention applies and electrical characteristics of theconventional technique, in which FIG. 2A shows a drive current (Ion)characteristics, FIG. 2B shows a threshold voltage characteristics andFIG. 2C shows subthreshold (SS) characteristics;

FIGS. 3A to 3F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 3A is a plan view, FIG. 3B is a crosssectional view taken along an X1-X1 section line of FIG. 3A, FIG. 3C isa cross sectional view taken along an X2-X2 section line of FIG. 3A,FIG. 3D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 3A, FIG. 3E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 3A, and FIG. 3F is a cross sectional view taken along aY3-Y3 section line of FIG. 3A;

FIGS. 4A to 4F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 4A is a plan view, FIG. 4B is a crosssectional view taken along an X1-X1 section line of FIG. 4A, FIG. 4C isa cross sectional view taken along an X2-X2 section line of FIG. 4A,FIG. 4D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 4A, FIG. 4E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 4A, and FIG. 4F is a cross sectional view taken along aY3-Y3 section line of FIG. 4A;

FIGS. 5A to 5F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 5A is a plan view, FIG. 5B is a crosssectional view taken along an X1-X1 section line of FIG. 5A, FIG. 5C isa cross sectional view taken along an X2-X2 section line of FIG. 5A,FIG. 5D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 5A, FIG. 5E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 5A, and FIG. 5F is a cross sectional view taken along aY3-Y3 section line of FIG. 5A;

FIGS. 6A to 6F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 6A is a plan view, FIG. 6B is a crosssectional view taken along an X1-X1 section line of FIG. 6A, FIG. 6C isa cross sectional view taken along an X2-X2 section line of FIG. 6A,FIG. 6D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 6A, FIG. 6E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 6A, and FIG. 6F is a cross sectional view taken along aY3-Y3 section line of FIG. 6A;

FIGS. 7A to 7F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 7A is a plan view, FIG. 7B is a crosssectional view taken along an X1-X1 section line of FIG. 7A, FIG. 7C isa cross sectional view taken along an X2-X2 section line of FIG. 7A,FIG. 7D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 7A, FIG. 7E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 7A, and FIG. 7F is a cross sectional view taken along aY3-Y3 section line of FIG. 7A;

FIGS. 8A to 8F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 8A is a plan view, FIG. 8B is a crosssectional view taken along an X1-X1 section line of FIG. 8A, FIG. 8C isa cross sectional view taken along an X2-X2 section line of FIG. 8A,FIG. 8D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 8A, FIG. 8E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 8A, and FIG. 8F is a cross sectional view taken along aY3-Y3 section line of FIG. 8A;

FIGS. 9A to 9F are views indicative of an embodiment of one process of amethod of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 9A is a plan view, FIG. 9B is a crosssectional view taken along an X1-X1 section line of FIG. 9A, FIG. 9C isa cross sectional view taken along an X2-X2 section line of FIG. 9A,FIG. 9D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 9A, FIG. 9E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 9A, and FIG. 9F is a cross sectional view taken along aY3-Y3 section line of FIG. 9A;

FIGS. 10A to 10F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 10A is a plan view, FIG. 10B is a crosssectional view taken along an X1-X1 section line of FIG. 10A, FIG. 10Cis a cross sectional view taken along an X2-X2 section line of FIG. 10A,FIG. 10D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 10A, FIG. 10E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 10A, and FIG. 10F is a cross sectional view taken along aY3-Y3 section line of FIG. 10A;

FIGS. 11A to 11F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 11A is a plan view, FIG. 11B is a crosssectional view taken along an X1-X1 section line of FIG. 11A, FIG. 11Cis a cross sectional view taken along an X2-X2 section line of FIG. 11A,FIG. 11D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 11A, FIG. 11E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 11A, and FIG. 11F is a cross sectional view taken along aY3-Y3 section line of FIG. 11A;

FIGS. 12A to 12F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 12A is a plan view, FIG. 12B is a crosssectional view taken along an X1-X1 section line of FIG. 12A, FIG. 12Cis a cross sectional view taken along an X2-X2 section line of FIG. 12A,FIG. 12D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 12A, FIG. 12E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 12A, and FIG. 12F is a cross sectional view taken along aY3-Y3 section line of FIG. 12A;

FIGS. 13A to 13F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 13A is a plan view, FIG. 13B is a crosssectional view taken along an X1-X1 section line of FIG. 13A, FIG. 13Cis a cross sectional view taken along an X2-X2 section line of FIG. 13A,FIG. 13D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 13A, FIG. 13E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 13A, and FIG. 13F is a cross sectional view taken along aY3-Y3 section line of FIG. 13A;

FIGS. 14A to 14F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 14A is a plan view, FIG. 14B is a crosssectional view taken along an X1-X1 section line of FIG. 14A, FIG. 14Cis a cross sectional view taken along an X2-X2 section line of FIG. 14A,FIG. 14D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 14A, FIG. 14E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 14A, and FIG. 14F is a cross sectional view taken along aY3-Y3 section line of FIG. 14A;

FIGS. 15A to 15F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 15A is a plan view, FIG. 15B is a crosssectional view taken along an X1-X1 section line of FIG. 15A, FIG. 15Cis a cross sectional view taken along an X2-X2 section line of FIG. 15A,FIG. 15D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 15A, FIG. 15E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 15A, and FIG. 15F is a cross sectional view taken along aY3-Y3 section line of FIG. 15A;

FIGS. 16A to 16F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 16A is a plan view, FIG. 16B is a crosssectional view taken along an X1-X1 section line of FIG. 16A, FIG. 16Cis a cross sectional view taken along an X2-X2 section line of FIG. 16A,FIG. 16D is a cross sectional view taken along a Y1-Y1 section line ofFIG. 16A, FIG. 16E is a cross sectional view taken along a Y2-Y2 sectionline of FIG. 16A, and FIG. 16F is a cross sectional view taken along aY3-Y3 section line of FIG. 16A;

FIGS. 17A to 17F are views indicative of an embodiment of one process ofa method of manufacturing a semiconductor device to which the presentinvention applies, in which FIG. 17A is a plan view, FIG. 17B is a crosssectional view taken along an X1-X1 section line of FIG. 17A, FIG. 17Cis a cross sectional view taken along an X2-X2 section line of FIG. 17A;and

FIG. 18 is a bird's-eye view of an example of a semiconductor deviceaccording to the conventional technique.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention will be now described herein with referenceto illustrative embodiments. Those skilled in the art will recognizethat many alternative embodiments can be accomplished using the teachingof the embodiments of the present invention and that the invention isnot limited to the embodiments illustrated for explanatory purpose.

(Semiconductor Device)

The structure of a semiconductor device 100 will be described withreference to FIGS. 1A to 1C.

The semiconductor device 100 functions as a DRAM. As shown in FIG. 1A,the semiconductor device 100 includes a cell array region SA and aperipheral circuit region CA in a semiconductor substrate 1. A pluralityof memory cells are arranged in a matrix in the cell array region SA. Acircuit for controlling operations of each memory cell is disposed inthe peripheral circuit region CA. Each of the memory cells arranged inthe cell array region SA includes a selection transistor and a capacitorelectrically connected to any one of a source and a drain of theselection transistor.

In the cell array region SA, a plurality of isolation regions 3 and aplurality of active regions 1 a are alternately arranged in stripes. Theplurality of active regions 1 a are insulated and isolated by theisolation regions 3 a. The plurality of isolation regions 3 a are formedas follows. A plurality of isolation trench portions 2 extending in anX′ direction (a first direction) are formed in the semiconductorsubstrate 1. The plurality of isolation regions 3 a called shallowtrench isolation (STI) are formed by burying isolation insulating films3 in the plurality of isolation trench portions 2.

In the cell array region SA, a plurality of word lines 12 a (firstconductors) that extend in the Y direction (the second direction)intersecting with the isolation regions 3 a and the active regions 1 aare also arranged in the first direction in stripes. The word lines 12 aconstitute gate electrodes 12 a of the selecting transistors. The wordlines 12 a also constitute so-called buried gate electrodes 12 a thatare arranged in lower portions of gate electrode trench portions 9 cformed across the isolation regions 3 a and the active regions 1 a, witha gate insulating film 11 interposed between the gate electrodes 12 aand the gate electrode trench portions 9 c. The buried gate electrodes12 a are constructed from a conductive material (the first conductor)made of metal. In this case, among the gate electrode trench portions 9c extending in the second direction, portions formed to overlap theactive regions 1 a are referred to as first trench portions 9 andportions formed to overlap the isolation regions 3 a are referred to assecond trench portions 10. Each of the first trench portions 9 has sidesurfaces of the semiconductor substrate 1 that constitutes the activeregions 1 a facing with each other. As shown in FIG. 1A, a width W2 inthe first direction of the second trench portions 10 located in theisolation regions 3 a is larger than a width W1 in the first directionof the first trench portions 9 located in the active regions 1 a.Therefore, the trench portions 9 c for the buried gate electrodesincluding the first trench portions 9 and the second trench portions 10alternately and repeatedly arranged and extending in the Y direction(the second direction) have a double-edged saw configuration in a planarview. Accordingly, the buried gate electrodes 12 a buried in the lowerportions of the trench portions 9 c also have a double-edged sawconfiguration in a planar view. Furthermore, a cap insulating film(explained later) that covers upper surfaces of the buried gateelectrodes 12 a to bridge the trench portions 9 c also has aconfiguration including a double-edged saw shape in a planar view.

Turning to FIG. 1B, specifically, in the cell array region SA, first finportions 30 a, which are portions of the active regions 1 a protrudingfrom between bottom surfaces 3 cc of adjacent ones of the second trenchportions 10, are provided by setting a position in a depth direction ofthe bottom surfaces 3 cc of the second trench portions 10 formed in theisolation regions 3 a among the gate electrode trench portions 9 c to bedeeper than a position in the depth direction of bottom surfaces 1 ac ofthe first trench portions 9 formed in the active regions 1 a, and pairsof second fin portions 30 b, which are portions of the active regions 1a protruding from between entire side surfaces 70 of adjacent ones ofthe second trench portions 10 to be continuous with the first finportions 30 a, are provided by setting a position in the first directionof the entire side surfaces 70 of the second trench portions 10 backfrom a position of entire side surfaces 1 aa of the first trenchportions 9. Each of the second fin portions 30 b is configured to beconnected to either end in the first direction of the first fin portion30 a extending in the first direction and to extend in a directionperpendicular to an upper surface of the first fin portion 30 a. Theentire side surface 70 of the second trench portion 10 indicates a sidesurface including a side surface 3 ca of an element isolation insulatingfilm 3 that constitutes the isolation regions 3 a and a side surface 7aa of a mask insulating film 7 provided across upper surfaces of theisolation regions 3 a and the active regions 1 a. The side surface 3 caof the element isolation insulating film 3 and the side surface 7 aa ofthe mask insulating film 7 are configured to be flush. The upper surfaceof the element isolation insulating film 3 and the upper surfaces of theactive regions 1 a are configured to be flush. In the presentembodiment, the mask insulating film 7 is preferably made of a materialhaving the same etching rate as that of the element isolation insulatingfilm 3. Preferably, these films are made of the same material to obtainthe same etching rate. For example, when the element isolationinsulating film is made of a silicon dioxide film, the mask insulatingfilm is also made of the silicon dioxide film. When the elementisolation insulating film is made of a silicon nitride film, the maskinsulating film is also preferably made of the silicon nitride film.However, the present invention is not limited thereto. It suffices thatthe element isolation insulating film and the mask insulating film hasthe same etching rate and these films do not need to be made of the samematerial.

Turning to FIG. 1C, the first fin portion 30 a constitutes a firstchannel region 30 a with the width W1 in the first direction, which isformed by causing the bottom surface 1 ac of the first trench portion 9to protrude from between the bottom surfaces 3 cc of adjacent ones ofthe second trench portions 10 by a difference ΔD (=D2−D1) between adepth D1 of the bottom surface 1 ac of the first trench portion 9 fromthe upper surface 1 b of the active region 1 a and a depth D2 of thebottom surface 3 cc of the second trench portion 10 from the uppersurface 1 b of the active region 1 a.

A pair of the second fin portions 30 b is formed by protruding entireside surfaces of the first trench portion 9 adjacent to the second finportions 30 b in the second direction from between entire side surfaces70 by half (ΔW) a difference 2ΔW (=W2−W1) between the width W1 of thefirst trench portion 9 and the width W2 of the second trench portion 10in the first direction. Thereby, second channel regions which extend ina direction perpendicular to the upper surface 1 b of the active region1 a from both ends of the first fin portion 30 a in the first directionare formed. Width of the second channel regions in the first directionis ΔD.

As shown in FIG. 1A, one side surface 9 ca extending in the seconddirection of the gate electrode trench portion 9 c extending in thesecond direction has a side surface obtained by continuously andrepeatedly arranging in the second direction a basic side surface, whichis a continuous side surface consisting of the side surface 3 ca of thesecond trench portion 10 extending in the second direction, one sidesurface lad of the second fin portion 30 b connected to one end of theside surface 3 ca and extending in the first direction, the side surface1 aa of the first trench portion 9 connected to an end of the sidesurface 1 ad on a side opposite to an end connected to the side surface3 ca and extending in the second direction, and the other side surface 1ae of the second fin portion 30 b connected to an end of the sidesurface 1 aa on a side opposite to an end connected to the side surface1 ad and extending in the first direction. The other side surface 9 cbopposite to the side surface 9 ca has a similar configuration.

The semiconductor device 100 may include the gate insulating film 11covering the surfaces of the first and second fin portions 30 a and 30b. The gate electrode 12 a is buried in gate electrode trench portion 9c so as to cross over the first fin portion 30 a and a part of thesecond fin portion 30 b. Therefore, the semiconductor device 100 has asaddle fin channel structure on not only the bottom surface but also theside surface . . . .

In parts of the active regions 1 a between which the gate electrode 12 ais interposed, the drain region 6 a and the source region 6 b (impuritydiffusion layers) are respectively provided by implanting ions. Thedrain region 6 a and the source region 6 b function as a source and adrain of the selection transistor, respectively. The drain region 6 aand the source region 6 b have bottoms which are connected to the topsof the second fin portions 30 b, which are located under the drainregion 13 a and the source region 13 b, respectively. The upper surfaceof the gate electrode 12 a mentioned above is provided at position notto overlap with the side surfaces of the source region 6 a and the drainregion 6 b in a horizontal direction parallel to the upper surface 1 bof the semiconductor substrate 1.

The gate electrode 12 a is buried in the first and second trenchportions 9 and 10 extending in the second direction. The gate electrode12 a is interposed between the drain region 6 a and the source region 6b. The drain region 6 a and the source region 6 b respectively haveupper surfaces in positions that are higher in level than the uppersurface of the gate electrode 12 a. The pair of second fin portions (thesecond channel regions) 30 b is continuously connected to the respectivebottom surfaces of the drain region 6 a and the source region 6 b. Thepair of second fin portions (the second channel regions) 30 b extendssubstantially in the depth direction that is vertical to the uppersurface 1 b of the semiconductor substrate 1 from the respective bottomsurfaces of the drain region 6 a and the source region 6 b. One of thepair of second fin portions 30 b has first and second side surfacesopposed to each other and a third side surface adjacent to the first andsecond side surfaces. The other of the pair of second fin portions 30 bhas fourth and fifth side surfaces opposed to each other and a sixthside surface adjacent to the fourth and fifth side surfaces. The thirdand sixth side surfaces face toward each other. The distance between thethird and sixth surfaces is smaller than the width of a lower portion ofthe second trench portion 10. The first fin portion 30 a is connected tolower portions of the pair of second fin portions 30 b. The first finportion 30 a extends in the first direction between the pair of secondfin portions 30 b. The gate insulating film 11 covers the surfaces ofthe first and second fin portions 12 a and 12 b. The gate insulatingfilm 11 covers the first through sixth side surfaces. The gate electrode12 a contacts the gate insulating film 11. The gate electrode 12 a facestoward the first through sixth side surfaces while the gate insulatingfilm 11 being interposed between the gate electrode and the firstthrough sixth side surfaces. The semiconductor device 100 has a buriedgate transistor.

In the semiconductor device 100 having the above-described structure,electric charges released from the drain region 6 b propagate throughone second fin portion 30 b, the first fin portion 30 a, and the othersecond fin portion 30 b and then enter into the source region 6 a.

In the semiconductor device 100 according to the present embodiment isapplied as described above, the pair of second fin portions (the secondchannel regions) 30 b are provided to extend substantially in thedirection vertical to the upper surface 1 b of the semiconductorsubstrate 1 from both ends of the first fin portion (the first channelregion) 30 a. Therefore, all the channel regions can be configured bythe saddle fin channel structure.

Thus, it is possible to increase the ON current I_(on) by reducing theresistance of the entire channel compared to the conventional techniquein which only the bottom portion has the saddle fin channel structure.

FIGS. 2A to 2C show results of comparison of electrical characteristicsbetween the buried gate transistor using a saddle fin structure only atthe bottom surfaces of the trench portions according to the conventionaltechnique as shown in FIG. 18 and the buried gate transistor accordingto the present invention in which an entire channel region on the bottomand side surfaces of the trench portions forms a saddle fin structure.The abscissa axes represent the height of a bottom fin portion,mentioned above and denoted by ΔD. As the present invention, results ofa transistor having a side fin portion with ΔW (=ΔD) in addition to thebottom fin portion are shown. FIG. 2A shows the magnitude of a drivecurrent Ion, in which a larger value indicates better characteristics.While the drive current has a range of 21 to 21.5 μA in the conventionaltechnique, the transistor of the present invention has a higher range of24 to 24.5 μA, indicating improvement by about 20%. FIG. 2B shows themagnitude of a threshold voltage and FIG. 2C shows subthreshold (SS)characteristics, in both of which a smaller value indicates bettercharacteristics. It is indicated that the threshold voltage is reducedby about 15% and the SS characteristics are reduced by about 10% whencompared on a condition that the height of the fin portion is 10 nm. Thetransistor of the present invention can contribute to a high speedoperation and a low-power consumption operation of a semiconductordevice because of effects mentioned above.

In the cell array region SA shown in FIG. 1A described above, a numberof the isolation regions 3 a and the active regions 1 a as describedabove may be arranged and formed. For the sake of simplicity, FIG. 1Aschematically shows that some isolation regions 3 a and some activeregions 1 a are arranged and formed in the cell array region SA.

In the semiconductor device 100, although not shown, two buried wordlines 12 a operating for a normal transistor and a dummy word line aredisposed next to the buried word lines 12 a. The dummy word line is aburied wiring for isolation (a dummy gate). A predetermined potential isapplied to the dummy word line, so that adjacent transistors on the sameactive region are isolated. Alternatively, the parasitic transistor isin an OFF state and isolated by applying the predetermined potential tothe dummy word line. The dummy word wiring is formed as follows. Thetrench portions having the same configuration as the word lines 12 a aresimultaneously formed. A conductive material is buried in the trenchportions.

(Method of Manufacturing a Semiconductor Device)

A method of manufacturing the semiconductor device 100 will be describedwith reference to FIGS. 3A to 17C. In FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A,10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A, X1-X1 section line, X2-X2section line, Y1-Y1 section line, Y2-Y2 section line, and Y3-Y3 sectionline show a cross section of an active region 1 a that extends in thefirst direction, a cross section of an isolation region 3 a that extendsin the first direction, a cross section of a buried gate electrode thatextends in the second direction, a cross section of source/draindiffusion layers that are formed in the second direction, and a crosssection of a boundary region crossing over a cell array region SA and aperipheral circuit region CA, respectively.

In the cell array region SA shown in FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A,10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A, the isolation regions 3 aand the active regions 1 a as described above are arranged and formed inplural. However, a state in which some isolation regions 3 a and someactive regions 1 a arranged and formed in the cell array region SA areenlarged is schematically shown for convenience in FIGS. 3A, 4A, 5A, 6A,7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A.

Referring now to FIGS. 3A to 3F, a semiconductor substrate 1 is preparedbefore processing. The semiconductor substrate 1 may be, but is notlimited to, a single crystal substrate containing a predeterminedconcentration of p-type impurities, for example, a silicon singlecrystal substrate containing impurities.

The isolation regions 3 a extending in the first direction and theactive regions 1 a sandwiched by the isolation regions 3 a are firstformed on a surface of the semiconductor substrate 1 using a known STImethod. More specifically, a silicon nitride film (not shown) and a maskfilm on the silicon nitride film are formed. A mask pattern to open theisolation regions 3 a is then formed on the mask film by lithography andan anisotropic dry etching method. The mask pattern is then transferredto the silicon nitride film by the anisotropic dry etching method usingthe mask film as a mask, thereby exposing the surface of thesemiconductor substrate 1 in the isolation regions 3 a. The mask film isthen removed to expose the silicon nitride film. The semiconductorsubstrate 1 is then subject to anisotropic dry etching using the exposedsilicon nitride film as a mask, thereby forming element isolationtrenches 2, which are 280-nm deep, for example. The element isolationinsulating film 3 is then formed all over to fill the element isolationtrenches 2. A silicon dioxide film or a silicon nitride film is used forthe element isolation insulating film 3. In this case, the silicondioxide film is used therefor. A silicon film that is formed by aflowable CVD method or a spin coating method and then modified by heattreatment in an oxidizing atmosphere can be used as the silicon dioxidefilm. An HDP (High Density Plasma)-CVD method can be alternatively used.When the silicon nitride film is used, the film can be formed by usingan ALD (Atomic Layer Deposition) method. Because the isolation regions 3a formed in the peripheral circuit region have larger areas than thosein the memory cell area, a method that enables to first form the elementisolation insulating film in the memory cell area and then laminate thesilicon dioxide film by the HDP-CVD method to fill the wider isolationregions in the peripheral circuit region is used.

After the element isolation insulating film 3 is formed all over, theelement isolation insulating film 3 is etched back by using a CMP(Chemical Mechanical Polishing) method or a dry etching method, andfurther the silicon nitride film used as the mask is removed using a hotphosphoric acid, thereby forming the isolation regions 3 a with theelement isolation insulating film 3 filled in the element isolationtrenches 2. In this way, the isolation regions 3 a extending in the X′direction (the first direction) and the active regions 1 a sandwiched bythe isolation regions 3 a are formed alternately at a regular pitchdistance in the Y direction (the second direction) in the cell arrayregion SA, as shown in FIG. 3A. In this case, widths in the Y directionof the isolation regions 3 a and the active regions 1 a are 30 nm.

Turning to FIGS. 4A to 4F, a first gate insulating film 4 composed of asilicon dioxide film of 3-nm thick is formed on the surface of thesemiconductor substrate 1 (the surfaces of the active regions 1 a)exposed through the element isolation insulating film 3 by a thermaloxidation method. A non-doped amorphous silicon film 15-nm thick is thenformed allover the semiconductor substrate 1. Subsequently, n-typeimpurities (such as phosphorous) are ion-implanted all over the surfacelayer of the semiconductor substrate 1 via the non-doped silicon film.The n-type impurities are controlled to have a density of 1E19 to 5E19(atoms/cm³). Heat treatment is then performed at 1000° C. for 10seconds. This forms an n-type impurity diffused layer 6 on the surfacesof the active regions 1 a and also transforms the amorphous silicon filmto a polycrystalline silicon film (first silicon film) 5. The heattreatment can be performed at any later step. The impurity diffusedlayers 6 function as the source regions 6 a and the drain regions 6 b ofthe semiconductor device 100. The impurity diffused layers 6 are formedto have a depth of 50 nm from the surface 1 b of the semiconductorsubstrate 1.

Turning to FIGS. 5A to 5F, a photoresist pattern (not shown) that coversthe peripheral circuit region CA is formed by lithography to expose anupper surface of the polycrystalline silicon film 5 formed in the cellarray region SA. The polycrystalline silicon film 5 exposed in the cellarray region SA is then removed by the dry etching method using thephotoresist as a mask. The photoresist mask is then removed.Accordingly, the polycrystalline silicon film 5 remains on the uppersurface of the semiconductor substrate 1 in the peripheral circuitregion CA with the first gate insulating film 4 interposed therebetween.The polycrystalline silicon film (first silicon film) 5 functions as aprotection film for avoiding side effects on the peripheral circuitregion CA at a later step of forming the cell array region SA. Thepolycrystalline silicon film 5 also functions as a part of a gateelectrode in each planar transistor formed in the peripheral circuitregion CA.

Turning to FIGS. 6A to 6F, a mask insulating film 7 composed of asilicon dioxide film 40-nm thick is formed all over the semiconductorsubstrate 1 by a plasma CVD method. A hard mask film 8 composed of anamorphous carbon film, an antireflection film, or the like is thenformed. While the first gate insulating film 4 is formed on the uppersurfaces of the active regions 1 a in the cell array region SA at thisstage, the first gate insulating film 4 has a quite small thickness of 3nm, and therefore it is omitted in the following drawings as beingcombined with the mask insulating film 7.

While the same silicon dioxide film as that of the element isolationinsulating film 3 is used for the mask insulating film 7 in the presentembodiment, a problem mentioned below occurs if a silicon nitride filmis used for the mask insulating film 7, for example. When wet etchingwith an HF-containing solution is performed at a stage shown in FIGS.10A to 10F as a later step to form a saddle fin structure, only theelement isolation insulating film 3 is set back and the silicon nitridefilm that covers the upper surface of the element isolation insulatingfilm 3 remains like eaves because an etching rate of the silicon nitridefilm is lower than that of the silicon dioxide film constituting theelement isolation insulating film 3. That is, an opening mouth has awidth smaller than the internal width W2 of a third opening 9 c. If agate electrode to be buried is formed in this state, the opening mouthis closed before inside and thus a void is produced therein. That is,the gate electrode is insufficiently buried and resistance is increased.Therefore, in the present embodiment, it is necessary to selectmaterials that can be etched at the same rate for the element isolationinsulating film 3 and the mask insulating film 7. Alternatively, it isnecessary to select an etching method that enables to etch the elementisolation insulating film 3 and the mask insulating film 7 at the samerate even when different materials are used therefor.

Turning to FIGS. 7 a to 7F, a photoresist pattern (not shown) is formedby lithography. The photoresist pattern is formed as a line patternextending in the Y direction across the active regions 1 a and theisolation regions 3 a extending in the first direction. A width L1 inthe first direction of the line pattern is 30 nm, for example, and thewidth W1 in the first direction of openings is 30 nm, for example. Thehard mask film 8 is then etched by the anisotropic dry etching methodusing the photoresist pattern as a mask to transfer the line pattern.The photoresist pattern is then removed. Further, the mask insulatingfilm 7 located therebeneath is subject to the anisotropic dry etching toform a mask film 8 a composed of the hard mask film 8 and the maskinsulating film 7. In this way, first openings 9 a with the width W1 of30 nm are formed between adjacent portions of the mask film 8 a. Theupper surfaces of the n-type impurity diffused layers 6, that is, theupper surfaces 1 b of the active regions 1 a and the upper surfaces ofthe isolation regions 3 a are alternately exposed in the Y direction atthe bottoms of the first openings 9 a.

Turning to FIGS. 8A to 8F, the active regions 1 a and the isolationregions 3 a having the upper surfaces exposed are etched by theanisotropic dry etching method using the mask film 8 a as a mask,thereby forming second openings 9 b. A depth D1 of the second openings 9b from the upper surfaces 1 b of the active regions 1 a is 180 nm, forexample. While the isolation regions 3 a and the active regions 1 a canbe simultaneously etched by the anisotropic dry etching, it is morepreferable that the isolation regions 3 a are first etched and then theactive regions 1 a are etched. At a stage in which the isolation regions3 a that are 280-nm deep are formed on the semiconductor substrate 1,boundary surfaces between the isolation regions 3 a and adjacent activeregions 1 a are formed to be slightly inclined toward the active regions1 a. Therefore, if the active regions 1 a are first subject to theanisotropic dry etching, the isolation regions 3 a constituting theinclined boundary surfaces adversely serve as masks and thus portions ofthe active regions 1 a extending in the first direction under thesemasks remain unetched. Accordingly, a method of first performing theanisotropic dry etching of the active regions 1 a and then performingthe anisotropic dry etching of the isolation regions 3 a is unfavorable.It is preferable that the active regions 1 a and the isolation regions 3a are simultaneously etched or the isolation regions 3 a are firstsubject to the anisotropic dry etching, as mentioned above. In theanisotropic dry etching of the element isolation insulating film 3composed of the silicon dioxide film, gas plasma containing high-orderfluorocarbon such as octafluorocyclobutane (C₄F₈) is used. In theanisotropic dry etching of the active regions 1 a composed of silicon,gas plasma containing hydrogen bromide (HBr), chlorine (Cl₂), or oxygen(O₂) is used. By forming the second openings 9 b, the impurity diffusedlayers 6 are divided into the source regions 6 a and the drain regions 6b.

Turning to FIGS. 9A to 9F, among the mask film 8 a used as the mask forforming the second openings 9 b, the hard mask film 8 is selectivelyremoved by dry etching using oxygen gas plasma. Accordingly, in thesecond openings 9 b extending in the Y direction, first trench portions91 are formed at portions overlapping with the active regions 1 a andsecond trench portions 101 are formed at portions overlapping with theisolation regions 3 a. At this stage, each of the first trench portions91 consists of a first side surface composed of a side surface 7 a ofthe mask insulating film 7 and the side surface 1 aa of the activeregion 1 a, a second side surface opposite to the first side surface andcomposed of a side surface 7 b of the mask insulating film 7 and a sidesurface lab of the active region 1 a, and the bottom surface 1 accomposed of the active region 1 a. Each of the second trench portions101 consists of a first side surface composed of the side surface 7 a ofthe mask insulating film 7 and a side surface 3 ba of the isolationregion 3 a, a second side surface opposite to the first side surface andcomposed of the side surface 7 b of the mask insulating film 7 and aside surface 3 bb of the isolation region 3 a, and a bottom surface 3 bccomposed of the isolation region 3 a.

Turning to FIGS. 10A to 10F, the mask insulating film 7 and the elementisolation insulating film 3 exposed in the second openings 9 b aresimultaneously etched by using isotropic etching. Dotted lines 80 inFIG. 10 indicate surface profiles in cross sections before the isotropicetching is performed (the same holds true for FIGS. 9A to 9F). At thisetching step, a method that does not etch the silicon substrate 1exposed in the second openings 9 b needs to be used. If the siliconsubstrate 1 is etched together with the mask insulating film 7 and theelement isolation insulating film 3, a fin structure cannot be formed.Because the mask insulating film 7 and the element isolation insulatingfilm are made of the silicon dioxide film in the present embodiment, thesilicon dioxide film needs to be isotropically etched with a higherselectivity than the silicon. As the isotropic etching, any of (1) a wetetching method using a hydrofluoric acid (HF)-containing solution, (2)an isotropic dry etching method using the gas plasma containinghigh-order fluorocarbon mentioned above, and (3) a chemical dry etchingmethod using anhydrous hydrogen fluoride gas and ammonia gas can beused. In any method, an etching selectivity of the silicon dioxide filmrelative to the silicon can be 100 times or higher. For example, 0.1 nmor less of the silicon is etched during etching of 10 nm of the silicondioxide film and substantially no silicon is etched.

From a viewpoint of etching the element isolation insulating film 3 andthe mask insulating film 7 at the same rate, the element isolationinsulating film 3 and the mask insulating film 7 are preferably made ofthe same material in the wet etching method (1) and the isotropic dryetching method (2). In the case of the chemical dry etching method (3),the element isolation insulating film 3 and the mask insulating film 7can be made of different materials because, for example, the silicondioxide film and the silicon nitride film can be etched at the samerate.

The chemical dry etching (3) using the anhydrous hydrogen fluoride gasand the ammonia gas is explained in more detail. The semiconductorsubstrate is installed in a reaction chamber and then left for about 60seconds with a temperature kept in a range of 30 to 50° C. whilesupplying about 20 sccm of anhydrous hydrogen fluoride (HF) gas andabout 20 sccm of ammonia (NH₃) gas controlled under a pressureatmosphere of 20 mTorr. This forms sublimable ammonium fluorosilicate ona surface of the silicon dioxide film. When the temperature is raised to200° C. under an inert gas atmosphere of 650 mTorr, the ammoniumfluorosilicate is sublimated and removed. An amount of the silicondioxide film removed when the processing is performed once under thiscondition is 5 nm in thickness, which indicates that the silicon dioxidefilm can be removed with a quite high accuracy. While the silicondioxide film has been explained above as an example, the silicon nitridefilm can be similarly etched. Even when this processing is performed, noammonium fluorosilicate is formed on a surface of the silicon and thusthe silicon is not removed at all. Although the chemical dry etchingmethod itself is a known technique, it is an effective measure whenapplied to the saddle fin formation method of the present embodiment.

The wet etching method (1) of using the hydrofluoric acid(HF)-containing solution is explained below. This method can achieveideal isotropic etching. In addition, only the silicon dioxide film canbe selectively etched while the silicon is not etched. The temperatureis not particularly limited and can be a room temperature. Because beingboth made of the silicon dioxide film, the mask insulating film 7 andthe element isolation insulating film 3 can be etched at the same rate.In this example, 10 nm of the element isolation insulating film 3 andthe mask insulating film 7 covering the upper surface of the elementisolation insulating film 3 are etched.

Accordingly, the third openings 9 c extending in the second directionare formed. The third openings 9 c become the trench portions 9 c forthe buried gate electrodes. Focusing on the second trench portions 10formed in the isolation regions 3 a in the third openings 9 c, thebottom surface 3 bc before the wet etching is dug down (set back) by 10nm in the depth direction to constitute a new bottom surface 3 cc. Thatis, the new bottom surface 3 cc is located at a position set back by 10nm in the depth direction from the bottom surface 1 ac of the firsttrench portion 9, and portions of the silicon substrate 1 constitutingthe active regions 1 a protrude by ΔD (10 nm) from between adjacentportions of the new bottom surface 3 cc, thereby forming the first finportions 30 a. Therefore, while a depth D1 of the bottom surface 1 ac ofthe first trench portion 9 from the upper surface 1 b of thesemiconductor substrate 1 is maintained at 180 nm, a depth D2 of the newbottom surface 3 cc of the second trench portions 10 from the uppersurface 1 b of the semiconductor substrate 1 is 190 nm because there isa change AD of 10 nm.

Meanwhile, the first side surface 3 ba before the wet etching is setback by 10 nm in the first direction, thereby constituting a new sidesurface 3 ca. That is, the new side surface 3 ca is located at aposition set back by 10 nm in the first direction from the side surface1 aa of the first trench portion 9, and portions of the siliconsubstrate 1 constituting the active regions 1 a protrude by ΔW (10 nm)in the first direction from between adjacent portions of the new sidesurface 3 ca, thereby forming the second fin portions 30 b. Furthermore,the second side surface 3 bb before the wet etching is set back by 10 nmin the first direction, thereby constituting a new side surface 3 cb.That is, the new side surface 3 cb is located at a position set back by10 nm in the first direction from the side surface 1 ab of the firsttrench portion 9, and portions of the silicon substrate 1 constitutingthe active regions 1 a protrude by ΔW (10 nm) in the first directionfrom between adjacent portions of the new side surface 3 cb, therebyforming the second fin portions 30 b. The mask insulating film 7 is alsoetched by 10 nm and therefore the side surface 7 a constituting thefirst side surface before the etching is set back in the firstdirection, thereby forming a new side surface 7 aa flush with the newside surface 3 ca constituted by the element isolation insulating film3. The side surface 7 b constituting the second side surface before theetching is setback in the first direction, thereby forming a new sidesurface 7 bb flush with the new side surface 3 cb constituted by theelement isolation insulating film 3. Because the mask insulating film 7is etched also from the upper surface, the thickness thereof, which is40 nm at the time of formation, is reduced to 30 nm.

In the second trench portions 10, the width L1 of the lines and thewidth W1 of the second openings 9 b, which are both 30 nm at the stagebefore the etching, are changed by ΔW of 10 nm due to the etching, sothat a width L2 of the lines is 10 nm and a width W2 of the thirdopenings 9 c is 50 nm at a stage after the etching. Meanwhile, the widthL1 of the lines and the width W1 of the second openings 9 b in the firsttrench portions 9 do not change even after the etching. Therefore, aplanar profile of the buried gate electrode trench portions 9 c finallyformed has a double-edged saw shape.

Turning to FIGS. 11A to 11F, surfaces of the first and second finportions 30 a and 30 b exposed in the gate electrode trench portions 9 care thermally oxidized to form the gate insulating film 11 composed of asilicon dioxide film of 3-nm thick. A conducting material 12 composed ofmetal is then formed all over to fill the gate electrode trench portions9 c. The conducting material 12 is obtained by first forming a titaniumnitride film of 5-nm thick serving as a barrier layer by the CVD methodand then forming thereon a tungsten film of 30-nm thick by the CVDmethod. As described above, if the mask insulating film 7 remains likeeaves at the opening mouths of the third openings 9 c, voids (air gaps)are formed inside of the third openings 9 c after the tungsten film isformed, which increases an entire resistance of conducting materialsserving as the word lines. Furthermore, if there are voids, the tungstenfilm located under the voids and the silicon of the active regions 1 aare also etched at a subsequent etch-back step and thus a saddle finstructure (the first fin portions 30 a) cannot be formed at the bottom.However, because the method of etching the mask insulating film 7 andthe element isolation insulating film 3 at the same rate is used in thepresent embodiment, no eave of the mask insulating film 7 is producedand therefore no void occurs in the tungsten film, thereby avoiding theproblem mentioned above.

Turning to FIGS. 12A to 12F, the conducting material 12 is etched backby the dry etching method using gas plasma containing boron trichloride(BCl₃) and chlorine to dig into the third openings 9 c (the gateelectrode trench portions 9 c), thereby forming the buried gateelectrodes (first conductors) 12 a at the bottom of the gate electrodetrench portions 9 c. In the etching back, the upper surfaces of the gateelectrodes 12 a are formed at the positions not to overlap with the sidesurfaces of the source regions 6 a and the drain regions 6 b in thehorizontal direction parallel to the upper surface 1 b of thesemiconductor substrate 1. Because the depth of the source regions 6 aand the drain regions 6 b from the surface 1 b of the semiconductorsubstrate 1 is 50 nm, the upper surfaces of the gate electrodes 12 a areformed to be deeper than 50 nm and shallower than 60 nm from the suppersurface 1 b of the semiconductor substrate 1. At this stage, the gateelectrodes 12 a have a double-edged saw structure extending in the Ydirection in which the width W1 in the first direction of the firsttrench portions 9 in the active regions 1 a is 30 nm and the width W2 inthe first direction of the second trench portions 10 in the isolationregions 3 a is 50 nm in a planar view, as shown in FIG. 12A.

Turning to FIGS. 13A to 13F, a silicon nitride film is formed by the ALDmethod all over the semiconductor substrate 1 to cover the uppersurfaces of the gate electrodes 12 a and to fill the trench portions 9c. The silicon nitride film is then etched back to the upper surface 1 bof the semiconductor substrate 1 by the dry etching method using gasplasma containing trifluoromethane (CHF₃) and difluoromethane (CH₂F₂),thereby forming a cap insulating film 14. In this way, the capinsulating film 14 having the same double-edged saw shape as the gateelectrodes 12 a in a planar view is formed to cover the upper surfacesof the gate electrodes 12 a. A first interlayer insulating film 15composed of a silicon dioxide film is then formed and a surface thereofis planarized by the CMP method.

Turning to FIGS. 14A to 14F, the upper surfaces of the source regions 6a are exposed by using the lithography and the anisotropic dry etchingmethod, thereby forming bit-line contact trenches 16 extending in the Ydirection. Accordingly, the upper surfaces of the source regions 6 a,the upper surface of the element isolation insulating film 3, and partsof the upper surface of the cap insulating film 14 are exposed atbottoms of the bit-line contact trenches 16. In the anisotropic dryetching, gas plasma containing high-order fluorocarbon and oxygen isused.

Turning to FIGS. 15A to 15F, an amorphous phosphorus-doped silicon filmof 30-nm thick is formed all over the semiconductor substrate 1 to fillthe bit-line contact trenches 16 with a width in the first direction of30 nm. Heat treatment is then performed at 1000° C. for 10 seconds tocause the amorphous silicon film to become polycrystalline and activatephosphorus contained as impurities to become a conductor. Thephosphorus-doped silicon film formed on the upper surface of theinterlayer insulating film 15 is then removed by the CMP method.Accordingly, buried conductors (second conductors) 17 a that bridge thebit-line contact trenches 16 are formed. A silicon film (second siliconfilm) 17 b serving as a part of the gate electrode of each peripheralcircuit transistor is formed in the peripheral circuit region CA.

Turning to FIGS. 16A to 16F, a metallic film 18 a is formed all over thesemiconductor substrate 1. The metallic film 18 a is composed of atitanium silicide film formed by the CVD method, a titanium nitride filmformed by the CVD method, a tungsten silicide film formed by thespattering method, and a tungsten film formed by the spattering method.A cover insulating film 19 composed of a silicon nitride film is furtherlaminated on an upper surface of the metallic film 18. The coverinsulating film 19 and the metallic film 18 a are etched by lithographyand the anisotropic dry etching method, thereby forming bit lines 18extending in an X direction (third direction) perpendicular to the Ydirection (second direction). The buried conductors 17 a formed in thebit-line contact trenches 16 and having upper surfaces exposed are thenetched using the cover insulating film 19 as a mask. Accordingly,bit-line contact plugs 17 are formed beneath the bit lines 18 in thebit-line contact trenches 16. The bit lines 18 and the source regions 6a are connected via the bit-line contact plugs 17. Side surfaces of thebit lines 18 facing in the Y direction and side surfaces of the bit-linecontact plugs 17 facing in the Y direction are flush. In the peripheralcircuit region CA, a gate electrode 20 of each planar transistor isformed of a first gate electrode 17 c composed of the first silicon film5 and the second silicon film 17 b, and a second gate electrode composedof the metallic film 18 a formed in the same layer as the bit lines 18.A photoresist pattern covering the cell array region SA is then formedand n-type impurities are implanted in the peripheral circuit region CAusing an ion implantation method, thereby forming a source diffusionlayer 21 and a drain diffusion layer 22 of each planar transistor.

Turning to FIGS. 17A to 17C, a side wall insulating film 23 thatprotects side walls of the bit lines 18 and the gate electrodes 20 inthe peripheral circuit region CA is formed and also a second interlayerinsulating film 24 is formed to cover the bit lines 18 and the planartransistors. Capacitive contact holes are then formed to expose theupper surfaces of the drain region 6 b by lithography and theanisotropic dry etching method. The capacitive contact holes are thenfilled with a third conductor to form capacitive contact plugs 25. Lowerelectrodes 26 connecting to the capacitive contact plugs are thenformed, a capacitive insulating film (not shown) is formed, an upperelectrode 27 is formed, a third interlayer insulating film is formed,contact plugs 29 are formed, and upper layer wirings 30 are formed,thereby manufacturing a DRAM semiconductor device.

While the height ΔD of the first fin portions 30 a extending in thedirection parallel to the upper surface of the semiconductor substrate 1and the width ΔW in the first direction of the second fin portions 30 bextending in the direction perpendicular to the upper surface of thesemiconductor substrate 1 are the same and 10 nm in the presentembodiment, the present invention is not limited thereto. In FIGS. 9A to9F, the element isolation insulating film 3 can be previously dug deeperthan the active regions 1 a by the anisotropic dry etching method at thestage of forming the second openings 9 b extending in the seconddirection, and then the isotropic etching can be performed to obtain theheight AD of the first fin portions 30 a larger than the width ΔW in thefirst direction of the second fin portions 30 b. For example, whenadditional etching of 10 nm is performed by the isotopic etching in astate where the bottom surface 3 bc of the element isolation insulatingfilm 3 is formed at a position that is 10 nm deeper than the bottomsurfaces 1 ac of the active regions 1 a at the stage of the anisotropicdry etching, the height ΔD of the first fin portions 30 a can be 20 nmand the width ΔW in the first direction of the second fin portions 30 bcan be 10 nm.

In addition, while not specifically claimed in the claim section, theapplicant reserves the right to include in the claim section of theapplication at any appropriate time the following devices:

A1. A semiconductor device comprising:

a plurality of element isolation regions extending in a first directionin parallel on a semiconductor substrate;

a plurality of active regions of the semiconductor substrate eachsandwiched between adjacent two of the element isolation regions;

a plurality of trenches extending in the second direction across theelement isolation regions and the active regions, each of the trencheshaving a plurality of first trench portions crossing the active regionsand a plurality of second trench portions crossing the element isolationregions, the first trench portions having bottom surfaces positioned athigher than bottom surfaces of the second trench portions so that eachof the active regions have a plurality of first fin portions formed onthe bottom surfaces of the first trench portions protruding with respectto the bottom surfaces of the second trench portions, and the secondtrench portions having a width in the first direction wider than a widthof the first trench portions in the first direction so that each of theactive regions have a plurality of second fin portions formed on sidesurfaces of the first trench portions protruding with respect to theside surfaces of the second trench portions;

a plurality of conductive films each buries a lower portion of anassociated one of the trenches; and

a plurality of cap insulating films each covers an upper surface of anassociated one of the conductive films so that the cap insulating filmsbury upper portions of the trenches.

A2. The semiconductor device as described in A1, further comprising aplurality of mask films extending in the second direction across theelement isolation regions and the active regions formed at outside ofthe trenches.

A3. The semiconductor device as described in A2, wherein the mask filmshave substantially constant width in the first direction.

A4. The semiconductor device as described in A2, wherein the mask filmscomprise substantially the same material as the element isolationregions.

A5. The semiconductor device as described in A2, wherein the mask filmsand the element isolation regions comprise a silicon dioxide.

A6. The semiconductor device as described in A2, wherein the mask filmscomprise different material from the cap insulating films.

A7. The semiconductor device as described in A6, wherein the mask filmscomprise a silicon dioxide, and the cap insulating films comprise asilicon nitride.

A8. The semiconductor device as described in A1, wherein the capinsulating film has substantially the same planer shape as that of theconductive film.

B1. A semiconductor device comprising:

first and second element isolation regions extending in a firstdirection;

an active region sandwiched between the first and second elementisolation regions in a second direction intersecting with the firstdirection;

a trench extending in the second direction formed in the first andsecond element isolation regions and the active regions;

a conductive film formed at a lower portion of the trench; and

a cap insulating film formed at an upper portion of the trench, the capinsulating film having substantially the same planer shape as that ofthe conductive film.

B2. The semiconductor device as described in B1, wherein

the trench has a first trench portions crossing the active regions andsecond trench portions crossing the first and second element isolationregions,

the first trench portion has bottom surface positioned at higher thanbottom surfaces of the second trench portions so that the active regionhave a first fin portion formed on the bottom surfaces of the firsttrench portions protruding with respect to the bottom surfaces of thesecond trench portions, and

the second trench portions have a width in the first direction widerthan a width of the first trench portion in the first direction so thatthe active region has second fin portions formed on side surfaces of thefirst trench portion protruding with respect to side surfaces of thesecond trench portions.

B3. The semiconductor device as described in B1, wherein the conductivefilm has an upper surface that is positioned lower than upper surfacesof the first and second element isolation regions.

B4. The semiconductor device as described in B3, wherein the capinsulating film has an upper surface that is positioned at substantiallythe same plane as the upper surfaces of the first and second elementisolation regions.

B5. The semiconductor device as described in B2, further comprising agate insulating film provided between the conductive film and the firstand second fin portions.

B6. The semiconductor device as described in B5, wherein the conductivefilm serves as a gate electrode of a field effect transistor, and thefirst and second fin portions serve as a channel region of the fieldeffect transistor.

What is claimed is:
 1. A manufacturing method of a semiconductor device,the method comprising: forming a plurality of element isolation regionsextending in a first direction in parallel on a semiconductor substrateso that a plurality of active regions each sandwiched between adjacenttwo of the element isolation regions are defined in the semiconductorsubstrate, each of the element isolation regions having an elementisolation insulating film filling an isolation trench formed in thesemiconductor substrate, and the active regions being arranged at apredetermined pitch in a second direction intersecting with the firstdirection; forming a plurality of gate trenches extending in the seconddirection across the element isolation regions and the active regions,each of the gate trenches having a plurality of first trench portionscrossing the active regions and a plurality of second trench portionscrossing the element isolation regions, the first trench portions havingbottom surfaces positioned at higher than bottom surfaces of the secondtrench portions so that each of the active regions have a plurality offirst fin portions formed on the bottom surfaces of the first trenchportions protruding with respect to the bottom surfaces of the secondtrench portions, and the second trench portions having a width in thefirst direction wider than a width of the first trench portions in thefirst direction so that each of the active regions have a plurality ofsecond fin portions formed on side surfaces of the first trench portionsprotruding with respect to the side surfaces of the second trenchportions; forming a plurality of conductive films each buries a lowerportion of an associated one of the gate trenches; and forming aplurality of cap insulating films each covers an upper surface of anassociated one of the conductive films so that the cap insulating filmsbury upper portions of the gate trenches.
 2. The manufacturing method ofthe semiconductor device as claimed in claim 1, wherein the forming thetrench portions includes: forming first openings extending in the seconddirection across the element isolation regions and the active regions byan anisotropic dry etching method so that the bottom and side surfacesof the first and second trenches are exposed; and etching the bottom andside surfaces of the second trenches by isotropic etching method.
 3. Themanufacturing method of the semiconductor device as claimed in claim 2,wherein the forming the first openings includes: forming a plurality ofmask films extending in the second direction across the elementisolation regions and the active regions; and etching the elementisolation regions and the active regions using the mask films as anetching mask so that the first openings are formed.
 4. The manufacturingmethod of the semiconductor device as claimed in claim 3, wherein themask films comprise substantially the same material as the elementisolation insulating films.
 5. The manufacturing method of thesemiconductor device as claimed in claim 4, wherein the mask films andthe element isolation insulating films comprise a silicon dioxide. 6.The manufacturing method of the semiconductor device as claimed in claim3, wherein the mask films comprise different material from the capinsulating films.
 7. The manufacturing method of the semiconductordevice as claimed in claim 6, wherein the mask films comprise a silicondioxide, and the cap insulating films comprise a silicon nitride.
 8. Themanufacturing method of the semiconductor device as claimed in claim 1,wherein the conductive films and the cap insulating films fill the gatetrenches.
 9. A manufacturing method of a semiconductor device, themethod comprising: forming first and second element isolation regionsextending in a first direction in a semiconductor substrate so that anactive region of the semiconductor substrate sandwiched between thefirst and second element isolation regions in a second directionintersecting with the first direction is defined; forming first andsecond films extending in the second direction over the first and secondelement isolation regions and the active region, each of the first andsecond films having a lower film and an upper film; anisotropic etchingthe first and second element isolation regions and the active regionusing the upper films as an etching mask so that a first trench portionis formed in the active region and second trench portions are formed inthe first and second element isolation regions; removing the upper filmsso that the lower films are exposed; and isotropic etching the first andsecond element isolation regions and the lower films so that a first finportion is formed on a bottom surface of the first trench portionsprotruding with respect to bottom surfaces of the second trenchportions, and so that second fin portions are formed on side surfaces ofthe first trench portions protruding with respect to side surfaces ofthe second trench portions.
 10. The manufacturing method of thesemiconductor device as claimed in claim 9, the method furthercomprising forming a conductive film in the first and second trenchportions.
 11. The manufacturing method of the semiconductor device asclaimed in claim 10, wherein the conductive film has an upper surfacethat is positioned lower than upper surfaces of the first and secondelement isolation regions.
 12. The manufacturing method of thesemiconductor device as claimed in claim 11, the method furthercomprising forming a cap insulating film on the conductive film.
 13. Themanufacturing method of the semiconductor device as claimed in claim 12,wherein the cap insulating film has an upper surface that is positionedat substantially the same plane as the upper surfaces of the first andsecond element isolation regions.
 14. The manufacturing method of thesemiconductor device as claimed in claim 12, wherein the cap insulatingfilm has substantially the same planer shape as that of the conductivefilm.
 15. The manufacturing method of the semiconductor device asclaimed in claim 9, wherein the lower films comprise substantially thesame material as the first and second element isolation regions.
 16. Themanufacturing method of the semiconductor device as claimed in claim 15,wherein the lower films and the first and second element isolationregions comprise a silicon dioxide.
 17. The manufacturing method of thesemiconductor device as claimed in claim 12, wherein the lower filmscomprise a silicon dioxide, and the cap insulating film comprising asilicon nitride.
 18. The manufacturing method of the semiconductordevice as claimed in claim 12, wherein the upper films comprise neithera silicon dioxide nor a silicon nitride.
 19. The manufacturing method ofthe semiconductor device as claimed in claim 10, the method furthercomprising forming a gate insulating film between the conductive filmand the first and second fin portions.
 20. The manufacturing method ofthe semiconductor device as claimed in claim 19, wherein the conductivefilm serves as a gate electrode of a field effect transistor, and thefirst and second fin portions serve as a channel region of the fieldeffect transistor.